ML-Based Macro-Modeling for SAR ADC Analog IC Design

MMM: Machine Learning-Based Macro-Modeling

Accelerating Performance Estimation for Linear Analog ICs and ADC/DACs

Yishuang Lin, Yaguang Li, Meghna Madhusudan, et al.

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The Bottleneck: Analog Design Automation

SPICE simulations are computationally expensive, slowing down optimization loops (days to weeks).

Existing ML Models (Flat P2M): Require massive training data (thousands of simulations) and lack reusability.

Symbolic Analysis & MOR: Limited to small or linear circuits; struggle with ADCs/DACs.

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The MMM Solution: Hierarchical Macro-Modeling

Decompose large circuits into standard reusable sub-circuits (e.g., OTA, Comparator).

Train Once, Reuse Everywhere: Models for sub-circuits are trained independently and assembled for system estimation.

Handling Complexity: Separate handling for Loading Effects, Feedback Loops, and Variable Inputs.

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Methodology: Linear Analog ICs

DC Voltage Modeling: ML models estimate DC operating points (considering loading effects).

Parametric Transfer Function: H(s) coefficients are predicted by ML models based on DC points and device sizes.

Pole/Zero Analysis

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Methodology: Time-Domain for ADCs

Unlike linear ICs, ADCs require discrete time-step evaluation to capture dynamic behavior.

Sequential Propagation: Output V(t) depends on Input V(t), Input V(t-1), and Output V(t-1).

Key Sub-circuits: Comparators and Encoders are modeled individually and linked.

Performance Output: FFT performed on time-domain waveform to extract SFDR and SNDR.

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Applying MMM to SAR ADCs

While initial results cover Flash/Pipeline ADCs, the MMM framework is naturally suited for Successive Approximation Register (SAR) architectures.

Comparator: Modeled via MMM Time-Domain interface (proven accurate in Flash results).

Capacitive DAC: Modeled similarly to Weighted Resistor DACs (linear passive network).

SAR Logic Loop: Digital feedback handled by system-level netlist assembly.

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Result: Modeling Accuracy

MMM achieves significantly lower error rates (<1%) compared to flat ANN and GNN approaches.

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Huge Reduction in Data Preparation Cost

For an 8-bit Flash ADC, MMM reduced simulation needs from 40 days to just 9.6 hours (due to sub-circuit reuse).

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Inference Speed: Replacing SPICE

MMM is orders of magnitude faster than SPICE for full-system verification.

8-bit ADC Evaluation Time: SPICE ~ 30 minutes vs MMM < 0.1 second.

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Conclusion & Future Work

MMM enables scalable, fast, and reusable performance modeling for Analog/Mixed-Signal ICs.

Achieved >1700x speedup in data prep and >3600x in inference speed over SPICE with <1% error.

Future Focus: Expanding the library for SAR ADCs and complex feedback loops in high-speed data converters.

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