# CPU Components and Functions: A-Level Computer Science
> Learn about the Fetch-Decode-Execute cycle, Von Neumann architecture, ALU, Control Unit, and CPU registers for OCR A-Level Computer Science.

Tags: computer-science, cpu-architecture, von-neumann, fetch-decode-execute, ocr-specification, registers, alu
## The Central Processing Unit (CPU)
* Overview of the CPU as the 'brain' of the computer.
* Performance metrics: Clock Speed (GHz), Core count, and Cache size.

## Von Neumann Architecture
* Stored Program Concept: Data and instructions share the same memory.
* Sequential execution managed by a single control unit.

## Internal Components: ALU and CU
* **Arithmetic Logic Unit (ALU):** Performs calculations (+, -, *, /) and logical comparisons (AND, OR, NOT, XOR).
* **Control Unit (CU):** Manages instruction execution, decoding, and coordinates components via control signals.

## Registers and Speed Hierarchy
* Registers are the fastest storage, followed by Cache and RAM.
* Memory Access Latency: Registers (~0.3ns), L1 Cache (~1ns), RAM (~14ns).

## Key CPU Registers
* **Program Counter (PC):** Next instruction address.
* **Accumulator (ACC):** Intermediate calculation results.
* **Memory Address Register (MAR):** Current address being fetched.
* **Memory Data Register (MDR):** Data/instruction after fetch or before write.
* **Current Instruction Register (CIR):** Holds the instruction being decoded.

## System Buses
* **Data Bus:** Bi-directional; carries data/instructions.
* **Address Bus:** Uni-directional; carries memory addresses.
* **Control Bus:** Bi-directional; carries command signals (Read/Write).

## Fetch-Decode-Execute Cycle
* **Fetch:** PC -> MAR -> Memory -> MDR -> CIR.
* **Decode:** CU interprets the instruction in the CIR.
* **Execute:** ALU or data transfer operation is performed.
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