# OCR A Level Computer Science Paper 1: CPU & System Revision
> Master OCR A Level Computer Science Paper 1 topics: Von Neumann architecture, FDE cycle, RISC vs CISC, memory management, and TCP/IP protocol stack.

Tags: ocr-a-level, computer-science, cpu-architecture, fetch-decode-execute, risc-cisc, networking, revision-guide
## Slide 1: OCR A Level Computer Science Paper 1
* Focus: Computer Systems intensive revision.
* Key Topics: CPU Architecture, Memory, Networks, & Data Structure.

## Slide 2: Von Neumann Model
* Shared Memory: Data and Instructions share the same address space.
* Shared Bus: Single set of data and address buses.
* Von Neumann Bottleneck: Instructions and data cannot be fetched simultaneously.

## Slide 3: Essential CPU Registers
* **PC**: Address of the next instruction.
* **MAR**: Address of current instruction/data to be fetched.
* **MDR**: Buffer for actual data/instruction from memory.
* **CIR**: Current instruction being decoded.
* **ACC**: Stores results of ALU operations.

## Slide 4: Fetch-Decode-Execute (FDE) Cycle
* **FETCH**: PC to MAR; Memory to MDR; MDR to CIR; PC incremented.
* **DECODE**: CU interprets instruction in CIR and identifies opcode.
* **EXECUTE**: Instruction performed by ALU or memory shift.

## Slide 5: CPU Performance Factors
* Clock Speed: GHz (cycles per second).
* Cores: Parallel execution via multithreading.
* Cache Size: High-speed local memory.

## Slide 6: CISC vs RISC
* **CISC**: Complex hardware, variable cycles, shorter code (e.g., Intel x86).
* **RISC**: Simple hardware, 1 cycle per instruction, longer code, enables pipelining (e.g., ARM).

## Slide 7: OS Memory Management
* **Paging**: Fixed-size physical divisions.
* **Segmentation**: Variable-size logical divisions.
* **Virtual Memory**: Use of secondary storage as RAM; risk of 'Thrashing'.

## Slide 8: Relational Databases & Normalization
* Relational Model: Tables linked by Primary and Foreign Keys.
* **1NF**: Atomic values.
* **2NF**: No partial dependencies.
* **3NF**: No transitive dependencies.

## Slide 9: TCP/IP Protocol Stack
1. **Application**: HTTP, SMTP, FTP.
2. **Transport**: TCP/UDP (packet sequencing).
3. **Network**: IP (routing).
4. **Link**: Ethernet/WiFi (MAC addresses).

## Slide 10: Boolean Algebra & Logic
* De Morgan’s Laws: ¬(A ∧ B) = ¬A ∨ ¬B and ¬(A ∨ B) = ¬A ∧ ¬B.
* Karnaugh Maps: Simplification tool using powers of 2.

## Slide 11: Floating Point Representation
* Format: Mantissa (sign + value) and Exponent (Two's Complement).
* Normalization: Maximizes precision; positive starts 01, negative starts 10.

## Slide 12: Practice Exam Question
* Question: Explain the FDE cycle involving registers (6 marks).
* Key steps: PC → MAR → Address Bus → Memory → Data Bus → MDR → CIR → PC Increment.
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